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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14046B Phase Locked Loop
The MC14046B phase locked loop contains two phase comparators, a voltage-controlled oscillator (VCO), source follower, and zener diode. The comparators have two common signal inputs, PCAin and PCBin. Input PCAin can be used directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. The self-bias circuit adjusts small voltage signals in the linear region of the amplifier. Phase comparator 1 (an exclusive OR gate) provides a digital error signal PC1out, and maintains 90 phase shift at the center frequency between PCAin and PCBin signals (both at 50% duty cycle). Phase comparator 2 (with leading edge sensing logic) provides digital error signals, PC2 out and LD, and maintains a 0 phase shift between PCA in and PCB in signals (duty cycle is immaterial). The linear VCO produces an output signal VCO out whose frequency is determined by the voltage of input VCO in and the capacitor and resistors connected to pins C1A, C1B, R1, and R2. The source-follower output SFout with an external resistor is used where the VCO in signal is needed but no loading can be tolerated. The inhibit input Inh, when high, disables the VCO and source follower to minimize standby power consumption. The zener diode can be used to assist in power supply regulation. Applications include FM and FSK modulation and demodulation, frequency synthesis and multiplication, frequency discrimination, tone decoding, data synchronization and conditioning, voltage-to-frequency conversion and motor speed control. * * * * * * Buffered Outputs Compatible with MHTL and Low-Power TTL Diode Protection on All Inputs Supply Voltage Range = 3.0 to 18 V Pin-for-Pin Replacement for CD4046B Phase Comparator 1 is an Exclusive Or Gate and is Duty Cycle Limited Phase Comparator 2 switches on Rising Edges and is not Duty Cycle Limited
L SUFFIX CERAMIC CASE 620 P SUFFIX PLASTIC CASE 648
DW SUFFIX SOIC CASE 751G
ORDERING INFORMATION
MC14XXXBCP MC14XXXBCL MC14XXXBDW Plastic Ceramic SOIC
TA = - 55 to 125C for all packages.
PIN ASSIGNMENT
LD PC1out PCBin VCOout INH C1A C1B 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD ZENER PCAin PC2out R2 R1 SFout VCOin
BLOCK DIAGRAM
SELF BIAS CIRCUIT PHASE COMPARATOR 1 PHASE COMPARATOR 2 VOLTAGE CONTROLLED OSCILLATOR (VCO) SOURCE FOLLOWER VSS
VSS
PCAin 14 PCBin 3 VCOin 9 VDD = PIN 16 VSS = PIN 8 INH 5
2 PC1out 13 PC2out 1 LD 4 11 12 6 7 VCOout R1 R2 C1A C1B
10 SFout 15 ZENER
REV 3 1/94
(c)MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995
MC14046B 1
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* Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: - 12 mW/_C From 100_C To 125_C
#Noise immunity specified for worst-case input combination. Noise Margin for both "1" and "0" level = 1.0 Vdc min @ VDD = 5.0 Vdc 2.0 Vdc min @ VDD = 10 Vdc 2.5 Vdc min @ VDD = 15 Vdc To Calculate Total Current in General: VCOin - 1.65 VDD - 1.35 3/4 VCOin - 1.65 3/4 IT 2.2 x VDD + 1 x 10-3 (CL + 9) VDD f + + + 1.6 x RSF R1 R2
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Total Supply Current (Inh = "0", fo = 10 kHz, CL = 50 pF, R1 = 1.0 M, R2 = RSF = , and 50% Duty Cycle)
Quiescent Current (Per Package) Inh = PCAin = VDD, Zener = VCOin = 0 V, PCBin = VDD or 0 V, Iout = 0 A
Input Capacitance
Input Current
Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc)
Input Voltage # (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc)
Output Voltage Vin = VDD or 0
Storage Temperature Range
Operating Temperature Range
Power Dissipation, per Package
DC Input Current, per Pin
Input Voltage, All Inputs
DC Supply Voltage
MC14046B 2
(VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Vin = 0 or VDD (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) 1 x 10-1 VDD2
[
Characteristic
Rating
R
100% Duty Cycle of PCAin
"1" Level
"0" Level
"1" Level
"0" Level
Source
Sink
100
Symbol
VOH
VOL
IOH
IDD
VIH
IOL
Iin Cin
VIL
IT
Symbol
VDD
Tstg
Vin
PD
TA
Iin
VDD Vdc
+ IQ
5.0 10 15
5.0 10 15
5.0 10 15
5.0 5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
15
--
- 0.5 to VDD + 0.5
- 65 to + 150
- 55 to + 125
where: IT in A, CL in pF, VCOin, VDD in Vdc, f in kHz, and R1, R2, RSF in M, CL on VCOout.
- 0.5 to + 18
- 1.2 - 0.25 - 0.62 - 1.8
4.95 9.95 14.95
0.64 1.6 4.2
Min
3.5 7.0 11
-- -- --
--
--
-- -- --
-- -- --
Value
10
500
- 55_C
0.1
0.05 0.05 0.05
Max
5.0 10 20
1.5 3.0 4.0
--
-- -- --
-- -- -- --
-- -- --
-- -- --
mAdc
Unit
mW
Vdc
Vdc
_C
_C
4.95 9.95 14.95
- 1.0 - 0.2 - 0.5 - 1.5
0.51 1.3 3.4
IT = (1.46 A/kHz) f + IDD IT = (2.91 A/kHz) f + IDD IT = (4.37 A/kHz) f + IDD
Min
3.5 7.0 11
-- -- --
--
--
-- -- --
-- -- --
0.00001
- 1.7 - 0.36 - 0.9 - 3.5
0.005 0.010 0.015
25_C
0.88 2.25 8.8
2.75 5.50 8.25
2.25 4.50 6.75
Typ
5.0
5.0 10 15
0 0 0
MOTOROLA CMOS LOGIC DATA
0.1 0.05 0.05 0.05 Max 5.0 10 20 7.5 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- - 0.7 - 0.14 - 0.35 - 1.1 4.95 9.95 14.95 0.36 0.9 2.4 Min 3.5 7.0 11 -- -- -- -- -- -- -- -- -- -- -- 125_C 1.0 0.05 0.05 0.05 Max 150 300 600 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- mAdc mAdc mAdc Adc Adc Unit Vdc Vdc Vdc Vdc pF
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* The formula given is for the typical characteristics only. ZENER DIODE SOURCE-FOLLOWER VOLTAGE CONTROLLED OSCILLATOR (VCO) PHASE COMPARATORS 1 and 2
ELECTRICAL CHARACTERISTICS* (CL = 50 pF, TA = 25C)
Dynamic Resistance (Iz = 1.0 mA)
Zener Voltage (Iz = 50 A)
Linearity (VCOin = 2.5 V 0.3 V, RSF > 50 k) (VCOin = 5.0 V 2.5 V, RSF > 50 k) (VCOin = 7.5 V 5.0 V, RSF > 50 k)
Offset Voltage (VCOin minus SFout, RSF > 500 k)
Input Resistance -- VCOin
Output Duty Cycle
Linearity (R2 = ) (VCOin = 2.5 V 0.3 V, R1 > 10 k) (VCOin = 5.0 V 2.5 V, R1 > 400 k) (VCOin = 7.5 V 5.0 V, R1 1000 k)
Temperature -- Frequency Stability (R2 = )
Maximum Frequency (VCOin = VDD, C1 = 50 pF R1 = 5.0 k, and R2 = )
DC Coupled -- PCAin, PCBin
Minimum Input Sensitivity AC Coupled -- PCAin C series = 1000 pF, f = 50 kHz
Input Resistance -- PCAin
Output Fall Time tTHL = (1.5 ns/pF) CL + 25 ns tTHL = (0.75 ns/pF) CL + 12.5 ns tTHL = (0.55 ns/pF) CL + 9.5 ns
Output Rise Time tTLH = (3.0 ns/pF) CL + 30 ns tTLH = (1.5 ns/pF) CL + 15 ns tTLH = (1.1 ns/pF) CL + 10 ns
MOTOROLA CMOS LOGIC DATA
-- PCBin Characteristic Symbol fmax tTHL tTLH Rin Rin Rin Vin RZ VZ -- -- -- -- -- -- 5 to 15 5 to 15 VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 15 15 -- -- Minimum Device 150 150 6.7 0.5 1.0 1.4 1.0 0.2 0.1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- See Noise Immunity Typical 0.12 0.04 0.015 1500 1500 1.65 1.65 1.65 100 200 400 700 100 50 37 180 90 65 7.0 0.1 0.6 0.8 1.0 1.0 1.0 0.7 1.4 1.9 2.0 0.4 0.2 50 300 600 1050 175 75 55 350 150 110 7.3 2.2 2.2 2.2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Maximum
Device
MC14046B 3
mV p-p Units %/_C MHz M M M ns ns % % % V V
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Note: These equations are intended to be a design guide. Since calculated component values may be in error by as much as a factor of 4, laboratory experimentation may be required for fixed designs. Part to part frequency variation with identical passive components is typically less than 20%. VCO output frequency (f). Center frequency (f0). Capture frequency range (2fC). Lock frequency range (2fL). Signal input noise rejection. Locks on harmonics of center frequency. Phase angle between PCAin and PCBin. No signal on input PCAin. Refer to Waveforms in Figure 3. Characteristic LD (Lock Detect) PC2out
MC14046B 4
PCAin PCAin Input Stage Input Stage PC1out XX XX PCBin PCBin 01 The frequency of VCOout, when VCOin = 1/2 VDD Depends on low-pass filter characteristics (see Figure 3). fC fL 90 at center frequency (f0), approaching 0_ and 180 at ends of lock range (2fL) VCO in PLL system adjusts to center frequency (f0). 0 0 00 11
Figure 1. Phase Comparators State Diagrams
The frequency range of the input signal on which the loop will lock if it was initially out of lock.
The frequency range of the input signal on which the loop will stay locked if it was initially in lock; 2fL = full VCO frequency range = fmax - fmin.
Figure 2. Design Information
fmax = Where: 10K R1 1M 10K R2 1M 100pF C1 .01 F fmin = Using Phase Comparator 1
PHASE COMPARATOR 2
PHASE COMPARATOR 1
10
0
R1(C1 + 32 pF)
R2(C1 + 32 pF)
00
11
v
vv vv vv
High
1
1
Yes
3-State Output Disconnected
10
+ fmin
00
11
1
01
(VCO input = VDD)
(VCO input = VSS)
Always 0_ in lock (positive rising edges).
VCO in PLL system adjusts to minimum frequency (fmin).
01
10
MOTOROLA CMOS LOGIC DATA
Using Phase Comparator 2 1 01 00 11 0 1 fC = fL Low No 10
9 VCOin PCAin @ FREQUENCY f PCBin 14 3 PHASE 2 OR 13 COMPARATOR PC1out OR PC2out EXTERNAL LOW-PASS FILTER 9 11 R1 EXTERNAL /N COUNTER R2
SOURCE FOLLOWER
10
SFout RSF
12
VCO 6 CIA CI
4 7 CIB
VCOout @ FREQUENCY Nf = f
Typical Low-Pass Filters
(a) INPUT R3 OUTPUT C2 2fC (a) INPUT R3 OUTPUT R4 (R3 C2 Typically: R4 C2 6N + fmax - 2
[p
1
2 pfL R3 C2
) 3, 000W) C2 + 100NDf fmax2
pD
N
f - R4 C2
f = fmax - fmin NOTE: Sometimes R3 is split into two series resistors each R3 / 2. A capacitor CC is then placed from the midpoint to ground. The value for CC should be such that the corner frequency of this network does not significantly affect n. In Figure B, the ratio of R3 to R4 sets the damping, R4 (0.1)(R3) for optimum results.
^
LOW-PASS FILTER
Filter A Definitions: N = Total division ratio in feedback loop K = VDD/ for Phase Comparator 1 K = VDD/4 for Phase Comparator 2 2 p D fVCO KVCO VDD - 2 V 2 p fr for a typical design n (at phase detector input) 10 0.707 Filter B
wn +
+
KfKVCO NR3C2 Nw
wn +
KfKVCO NC2(R3 R4)
)
^
^
z + 2K K n f VCO
F(s)
+ R3C21S ) 1
) KfKN ) VCO R3C2S ) 1 F(s) + S(R3C2 ) R4C2) ) 1
(R3C2
z + 0.5 wn
Waveforms Phase Comparator 1
PCAin VDD VSS VOH PCBin PC1out VCOin VOL VOH VOL VOH VOL VCOin Note: for further information, see: (1) F. Gardner, "Phase-Lock Techniques", John Wiley and Son, New York, 1966. (2) G. S. Moschytz, "Miniature RC Filters Using Phase-Locked Loop", BSTJ, May, 1965. (3) Garth Nash, "Phase-Lock Loop Design Fundamentals", AN-535, Motorola Inc. (4) A. B. Przedpelski, "Phase-Locked Loop Design Articles", AR254, reprinted by Motorola Inc. PCBin LD PC2out PCAin
Phase Comparator 2
VDD VSS VOH VOL VOH VOL VOH VOL VOH VOL
Figure 3. General Phase-Locked Loop Connections and Waveforms
MOTOROLA CMOS LOGIC DATA
MC14046B 5
OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE V
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 --- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01
-B-
1 8
C
L
-T-
SEATING PLANE
N E F D G
16 PL
K M J
16 PL
0.25 (0.010)
M
M
TB
S
0.25 (0.010)
TA
S
P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
B
1 8
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
MC14046B 6
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
-A-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
16
9
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
DIM A B C D F G J K M P R
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JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
MOTOROLA CMOS LOGIC DATA
*MC14046B/D*
MC14046B MC14046B/D 7

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